This invention relates generally to integrated circuit manufacture, and more particularly to the fabrication of conductive lines in integrated circuits.
Integrated circuits are formed on a semiconductor substrates such as silicon, germanium, or gallium-arsenide wafers. Active regions of the integrated circuits are formed in the semiconductor wafer itself. For example, the drain, source and channel of a metal-oxide field effect transistor (MOSFET) is formed in the surface of a semiconductor wafer. Active regions are coupled together and to various input and output pads by conductive lines formed over, but insulated from, the surface of the semiconductor wafer.
With reference to prior art FIG. 1a, after the active regions of the semiconductor wafer 10 have been formed, an insulating base oxide layer 12 is deposited over the surface of the wafer. Via holes (not shown) are etched through the oxide layer to provide a means for contacting the active regions of the wafer. Next, a "metallization" layer is deposited over the oxide layer and within the via holes. This metallization layer, which is typically aluminum (Al) or tungsten (W) is then etched to form conductive lines (such as a conductive line 14) between selected active regions of the wafer. Passivation or intermetal oxide, hereinafter referred to as a "passivation layer" is subsequently formed over the conductive line.
When the width of a conductive line becomes sufficiently small, e.g. approximately 2 microns, stress induced defects such as voids start to appear within the body of the conductive line. The origin of thermal stresses in conductive lines is discussed in the article "Finite Element Calculations of Thermal Stresses in Passivated and Unpassivated Lines Bonded to Substrates" by Sauter et al, Mat. Res. Soc. Syrup. Proc., Vol. 188, Material Research Society, 1990. These stresses are generated when the conductive lines are heated and then cooled while being constrained by the base oxide layer 12, or by both the base layer 12 and the passivation layer 16. For example, when a passivation layer 16 is deposited over a conductive line 14 by a chemical vapor deposition (CVD) process, the conductive line 14 is at 300.degree.-400.degree. C. during deposition and is then cooled to ambient temperatures after deposition.
With additional reference to FIG. 1b, even prior to the deposition of the passivation layer 16 the conductive line 14 is firmly adhered to the top of oxide layer 12 and the base of the conductive line is restrained from moving in an x-y plane. Heating and cooling results in the generation of tensile and compressive stresses in the conductive line. As seen in exaggerated detail in FIG. 1c, these stresses may result in bumps 17 during the heating of the line and defects such as voids 18 and faults 20 when the line is cooled.
This condition is worsened by the deposition of the passivation layer 16 over the conductive line 14. Now, the conductive line is not only constrained in the x-y plane, but is also constrained in the z direction as well. In consequence, the conductive line 14 is 3-dimensionally constrained, which can cause substantial internal stresses as the line is heated and cooled.
The problem of stress-induced defects becomes critical in sub-micron geometries. A conductive line with a great number of voids and other defects can break or can exhibit an unacceptably high resistance. Furthermore, stress-induced defects can exacerbate failures due to electromigration, i.e. due to the movement of atoms within the conductive line caused by, and in the direction of, electron flow. The electromigration effect can remove atoms from certain defect areas within the line, leading to premature failure of the conductive line at the defect areas.
Stress is also created by the diffusion of atoms of the conductive line into the surrounding oxide. Again, if sufficient numbers of atoms diffuse away from the conductive line, stress-induced defects such as voids can appear within the body of the conductive line. Stress-induced defects caused by diffusion are becoming more problematical as line widths continue to decrease. A discussion of this phenomenon can be found in a paper entitled "Al Diffusion into Glass Films Used for the Passivation of Fine Al Metallization" by A. Tanikawa, Journal of the Electrochemical Society, Volume 138, No. 10, October 1991, pp. 3047-3049.